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Low InP/dielectric interface trap density Dit will enable low subthreshold swings (SS) in mm-wave MOSFETs [1] using InGaAs/InP composite channels [2] for increased breakdown and in tunnel FETs (TFETs) [3] using InAs/InP heterojunctions [4] for increased tunneling probability. Reducing Dit at the etched InP mesa edges of DHBTs and avalanche photodiodes will reduce leakage currents and increase breakdown voltages. While it can be difficult [5] to extract Dit of III-V interfaces from MOSCAP characteristics, Dit can be readily determined from the SS of long gate length Lg MOSFETs. Here we report InP-channel MOSFETs with record low SS indicating record low Dit at the semiconductor-dielectric interface. The devices use a AlOxNy/ZrO2 gate dielectric and a 14nm channel thickness Tch. A sample of 13 MOSFETs at 2 m Lg shows SS=70mV/dec. (mean) ±3 mV/dec. (standard deviation), corresponding to a minimum Dit ~3×1012 cm-2eV-1. The lowest SS observed at 2 m Lg is 66 mV/dec. The results suggest that wide-bandgap InP layers can be incorporated into MOS device designs without large degradations in DC characteristics arising from interface defects